What is a FPGA Latch?

D latch

 

 You should never use a latch in your FPGA. Let's discuss what latch is and how they are generated in HDL code and learn how to avoid generating them accidentally. 

 

 The usual latch that is generated by the synthesis tools( The tools that convert your Verilog or VHDL code to low-level FPGA components) is the Gated D Latch. However, there are other types of latches. I suggeted that latches should be never be used because they are very dangerous. There are two main reasons for this

 

   1. Often the user who created the latch did so unintentionally. It is highly likely that the HDL code written is not         actually what the designer intended

   2. They can be very difficult for the FPGA tools to create properly. They add significant routing delays and can           cause you design to fail to meet timing

 

 Latch creation via incomplete assignment in combinational always block. You should always cover all your cases all your situations because you'll want to avoid latches.

 

 Processes or Always blocks are used in two main scenarios

   1. To define a block of combinational logic

   2. To define a block of sequential logic