Shift Register

Create delays and convert serial to parallel data in FPGAs

 Shift registers are a common FPGA building block. They are created by cascading Flip-Flops in a chain. All registers must share the same clock, the output of one register must be connected to the input of the next register in the chain. Shift registers are mainly used to accomplish one of three goals.

 

• Delaying data by some number of clock cycles
• Converting serial data to parallel data
• Converting parallel data to serial data

 

 Creating a shift register for delay

 Creating delay in an FPGA is the most common use of a shift register. The delay is often used to align data in time. The number of Flip-Flops in the delay chain dictates how many clock cycles it will take for the data on the input to propagate to the data on the output.  

 

 The code above demonstrates creating delay by passing data_to_delay to the least significant bit of shift. Then shift is continuosly shifted to the left on each clock cycle. This might be useful for example if you get some data in from one module, but don't want to act on it right away. In the code above, any bit from shift can be used to precisely control how much delay is applied, bit 0 has 1 bit of delay on it and bit 3 has 4 bits of delay.

 

 Converting serial data to parallel data

 Converting from serial data to parallel data is another common use of shift registers. This occurs when interfacing to off-chip signals that transmit data serially such as a UART receiver. When data comes in over a UART, it need to be converted from serial data 1-bit wide to a parallel byte that the FPGA can look at.

 

 

 Converting parallel data to serial data

 This is the opposite of the above and is used in UART transmitter. When you want to transmit a byte over UART, it must first be serialized and sent out over the single UART line. A shift register can be used for this purpose.