Synthesizable vs Non-Synthesizable code

 When you write VHDL or Verilog code, you are writing code that will be translated into gates, registers, RAMs, etc. The program that performs this task is known as a Synthesis Tool. It is the job of the Synthesis Tool to take your code and turn it into something that the FPGA can understand. However, there are some parts of VHDL and Verilog that the FPGA simpley can't implement. 

 

 Why would you have a language that contains code that in non-synthesizable? The reason is that it makes your testbenches more powerful. When you write a testbench for simulation, using non-synthesizable code constructs makes your testbench better and allows you to accomplish things easier.

 

 The most fundamental non-synthesizable piece of code is a delay statement. The FPGA has no cencept of time, so it is impossible to tell the FPGA to wair for 10 nanoseconds. Instead, you need to use clocks and Flip-Flops to accomplish your goals.